83006 / 51106 ms ot b8-7330 no.a0237-1/10 any and all sanyo semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. consult with your sanyo semiconductor representative nearest you before usingany sanyo semiconductor products described or contained herein in such applications. sanyo semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated val ues (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor products described or contained herein. LA72710V overview the LA72710V is a jpn mts (multi channel television sound) decoder. features ? with sif circuit, alignment-free stereo channel separation. ? separation is fine-tuned by input level adjustment. ? included filters are adjustment free. functions ? stereo & bilingual demodulate. ? stereo & bilingual detection. ? just clock out. ? built-in alc. specifications maximum ratings at ta = 25 c parameter symbol conditions ratings unit maximum supply voltage v cc max 9.6 v allowable power dissipation pd max ta 70 c ? 610 mw operating temperature topr -10 to +70 c storage temperature tstg -55 to +150 c ? when mounted on a 114.3 76.1 1.6mm 3 glass epoxy board. operating conditions at ta = 25 c parameter symbol conditions ratings unit recommended operating voltage v cc 9.0 v allowable operating voltage range v cc op 8.5 to 9.5 v orderin g number : ena0237 monolithic linear ic for jpn tv multi channel television sound decoder
LA72710V no.a0237-2/10 electrical characteristics at ta = 25 c, v cc = 9.0v ratings parameter symbol conditions min typ max unit current dissipation i cc no signal, inflow current at pin 19 40 50 60 ma input level v s in fc = 4.5mhz 80 90 100 db v mono output level v o mn fm = 1khz, 100% mod, pre-emphasis off -7.5 -6 -4.5 dbv mono l/r level difference ? v o mn fm = 1khz, 100% mod, pre-emphasis off -1.5 0 1.5 db mono distortion thdm fm = 1khz, 100% mod, pre-emphasis off 0.2 0.5 % mono frequency charac teristics fcm1 fm = 10khz/1khz, 100% mod, 15khz lpf pre-emphasis off -18 -14 db mono s/n snm non mod, 15khz lpf 50 db stereo output level v o st fm = 1khz, 100% mod, cue (stereo), 15khz lpf -7.5 -6 -4.5 dbv stereo distortion thds fm = 1khz, 100% mod, cue (stereo), 15khz lpf 0.7 1.5 % stereo s/n sns sub carrier (non mod), cue (stereo), 15khz lpf 45 db main output level v o ma fm = 1khz, 100% mod, cue (bilingual), 15khz lpf -7.5 -6 -4.5 dbv main distortion thdma fm = 1khz, 100% mod, cue (bilingual), 15khz lpf 0.3 1 % main s/n snma sub carrier (non mod), cue (bilingual), 15khz lpf 50 db sub output level v o su fm = 1khz, 100% mod, cue (bilingual), 15khz lpf -7.5 -6 -4.5 dbv sub distortion thdsu fm = 1khz, 100% mod, cue (bilingual), 15khz lpf 1 2 % sub frequency characte ristics fcsu fm = 10khz/1khz, 60% mod, cue (bilingual), 15khz lpf, pre-emphasis off -18 -14 db sub main s/n snsu sub carrier (non mod), cue (bilingual), 15khz lpf 45 db stereo separation l r sepr fm = 1khz (l-only), 60% mod, cue (stereo), 15khz lpf 30 35 db stero separation r l sepl fm = 1khz (r-only), 60% mod, cue (stereo), 15khz lpf 30 35 db stay behind carrier level clsu main = 0%, sub = 0% (carrier) cue (bilingual) -50 -40 dbv stay behind carrier level clma main = 0%, sub = 0% (carrier) cue (bilingual) -55 -45 dbv cross-talk main sub ctsub main: fm = 1khz, 100% modulation, cue (bilingual), 15khz lpf 35 45 db cross-talk sub main ctma sub: fm = 1khz, 100% modulation, cue (bilingual), 15khz lpf 45 55 db mode output mono modmo input = mono signal 0.7 1 1.3 v mode output stereo modst input = stereo signal 1.7 2 2.3 v mode output bilingual modbi input = bilingual signal 2.7 3 3.3 v just clock output high volt jch f = 400hz (mono), 40%mod 4 v just clock output low volt jcl f = 400hz (mono), 10%mod 1 v alc level v o alc mono 1khz mod 100% -11 -9.5 -8 dbv alc distortion thdalc mono 1k hz mod 100% 0.2 0.5 % [condition of input signal at pin 5] deviation of sif input mono: (fm = 400hz) 100% 4.5mhz 25khz pre-emphasis on. [output] l-ch : pin 14, r-ch : pin 13.
LA72710V no.a0237-3/10 package dimensions unit : mm 3315 block diagram and sample application circuit sanyo : ssop24j(275mil) 7.6 5.6 112 13 24 0.5 0.15 9.75 (1.3) 0.1 1.5max 0.8 (0.48) 0.3
LA72710V no.a0237-4/10 pin functions pin no. pin name function dc voltage ac level equivalent circuit 1 amdet reference terminal of am detection. 2 3 16 dcfil1 dcfil1 dcfil1 absorbing the dc offset of signal line by external capacity. dc: 2.4v 4 fmfil filter terminal for making stable dc voltage of fm detection output in sif part. normally, use a condenser of 1 f. increase the capacity value with concerning frequency characteristics of low level. 5 sifin input terminal for sif. the input impedance is about 5k ? . be care for about pattern layout of the input circuit, because of causing buzz-beat and buzz by leaking noise signal into the input terminal. (the noise signal depending on sound is particularly video signal and chroma signal and so on. vif carrier becomes noise signal.) 6 gnd 7 jcko 20db amplifier output for just clock. dc: 3.8v 8 cmpin comparator input fo r just clock. dc: 3.8v continued on next page
LA72710V no.a0237-5/10 continued from preceding page. pin no. pin name function dc voltage ac level equivalent circuit 9 jckrwo rectangle wave output for just clock. (open collector) 10 mute mute control terminal. mute: 2.8v to 11 sda serial data input / output terminal. high: 3.5v to 5v low: 0v to 1.5v 12 scl serial clock input terminal high: 3.5v to 5v low: 0v to 1.5v 13 rch line out (r) terminal. 14 lch line out (l) terminal. dc: 3.8v ac: -6dbv 15 alcdet alc detection terminal. 17 regfil filter terminal of re ference voltage source. dc: 4.5v continued on next page 5v 0v 0v 5v 0v 5v
LA72710V no.a0237-6/10 continued from preceding page. pin no. pin name function dc voltage ac level equivalent circuit 18 pcreg band gap source terminal block. dc: 1.2v 19 v cc power supply terminal. dc: 9v 20 mode detection output for m.t.s. signal. bilingual: 3.0v stereo: 2.0v mono: 1.0v 21 fscin input terminal for fsc (3.58mhz). ac: 200mvp-p 22 pllfil loop filter terminal. automatic adjusting for pll. 23 st phase comparator input (stereo). this detection pin becomes high (6.6v or more) when st signal is input. 24 bil phase comparator input (bilingal). this detection pin becomes high (6.6v or more) when bil signal is input.
LA72710V no.a0237-7/10 i 2 c bus serial interface specification (1) data transfer manual this ic adopts control method (i 2 c-bus) with serial data, and controlled by two terminals which called scl (serial clock) and sda (serial data). at first, set up *1 the condition of starting data transfer, and after that, input 8 bit data to sda terminal with synchronized scl terminal clock. the orde r of transferring is first, msb (the most scale of bit), and save the order. the 9th bit takes ack (acknowledge) peri od, during scl terminal takes ?h? this ic pull down the sda terminal. after transferred the necessary data, two terminals lead to set up and of *2 data transfer stop condition, thus the transfer comes to close. *1 defined by scl rise down sda during ?h? period. *2 defined by scl rise up sda during ?h? period. (2) transfer data format after transfer start condition, transfers slave address (1000 000 * b) to sda terminal, control data, then, stop condition (see figure 1). slave address is made up of 7bits, 8th bit *3 shows the direction of transferring data, if it is ?l? takes write mode (as this ic side, this is input operation mode), and in case of ?h? re ading mode (as this ic side, this is output operation mode). data works with all of bit, transfer the stop condition before stop 8bit transfer, an d to stop transfer, it will be canceled the transfer dates. *3 it is called r/w bit. fig.1 data structure ?write? mode start condition slave address r/wl ack control data ack stop condition fig.2 data structure ?read? mode start condition slave address r/wh ack internal data * ack stop condition ? output 8bits data as follows; bit8 is result of stero det (h : stereo) bit7 is result of bilingual det (h : bilingual) bit6 to bit1 are fixed to ?l? (3) initialize this ic is initialized for circuit protection. initial condition is ?0 (all bits).?
LA72710V no.a0237-8/10 i 2 c timing specifications parameter symbol min max unit low level input voltage v il -0.5 1.5 v high level input voltage v ih 3.0 5.5 v low level output current i ol 3.0 ma scl clock frequency f scl 0 100 khz set-up time for a repeated start condition t su:sta 4.7 s hold time start condition. after this peri od, the first clock pulse is generated t hd:sta 4.0 s low period of the scl clock t low 4.7 s rise time of both sda and sdl signals t r 0 1.0 s high period of the scl clock t high 4.0 s fall time of both sda and sdl signals t f 0 1.0 s data hold time t hd:dat 0 s data set-up time t su:dat 250 ns set-up time for stop condition t su:sto 4.0 s bus free time between a stop and start condition t buf 4.7 s i 2 c control conditions grp-1 (slave address 80h) d8 d7 d6 d5 d4 d3 d2 d1 condition 0 0 bilingual * 0 1 main 1 0 sub 1 1 (prohibit) * 0 normal 1 forced mono * 0 normal (mute off) 1 mute * 0 alc off (through) 1 alc on * 0 just clock off 1 just clock on * 0 sif mode 1 base band mode * 0 fix 1 prohibit (test mode) *:initial condition read out data d8 d7 d6 d5 d4 d3 d2 d1 condition 0 0 0 0 0 0 fixed 0 normal 1 bilingual det 0 normal 1 stereo det
LA72710V no.a0237-9/10 mode select (pin & i 2 c setting) mute i 2 c setting matrix out read mode out mode out broadcast signal pin10 d4 d3 d2 d1 lch (pin14) rch (pin13) mode d8 d7 pin20 l 0 0 0 0 main sub both l h l 0 0 0 1 main main main l h l 0 0 1 0 sub sub sub l h l 0 1 * * main main mono l h * 1 * * * mute mute mute l h bilingual h * * * * mute mute mute l h 3v l 0 0 * * l r stereo h l l 0 1 * * l+r l+r mono h l * 1 * * * mute mute mute h l stereo h * * * * mute mute mute h l 2v l 0 * * * l+r l+r mono l l * 1 * * * mute mute mute l l mono h * * * * mute mute mute l l 1v *: don?t care. serial data specification (i 2 c bus communication) msb lsb d8 d7 d6 d5 d4 d3 d2 d1 test sif or base band just clk alc normal out mute forced mono multiplex mode select 0:off 1:on 0:sif 1:base band 0:off 1:on 0:off 1:on 0:off 1:on 0:off 1:on 00:bilingual 01:main 10:sub 11:unusable note: underline shows default setting.
LA72710V ps no.a0237-10/10 test circuits specifications of any and all sanyo semiconductor pr oducts described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. to verify s ymptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. sanyo semiconductor co., ltd. strives to supply high- quality high-reliability products. however, any and all semiconductor products fail with some probabi lity. it is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property . when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any or all sanyo semiconductor produc ts (including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording , or any information storage or retrieval system, or otherwise, without the prior written permission of sanyo semiconductor co., ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the "delivery specification" for the sanyo semiconductor product that you intend to use. information (including circuit diagrams and circui t parameters) herein is for example only; it is not guaranteed for volume production. sanyo semicondu ctor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. this catalog provides informati on as of may, 2006. specifications and information herein are subject to change without notice.
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